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University of Auckland Lab 3 COMPSYS201 - 2020
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Lab 3: Simple Calculator – Register Transfer Level Design with
Datapath + Finite State Machine (FSM) based Control Unit
(3%)
Background
This simple calculator can perform three different operations: addition,
subtraction, and multiplication of two positive decimal numbers, where each
number can be up to two decimal digits (i.e. 00 to 99).
The actual hardware implementation uses some simple but common interfaces: a
4x4 matrix keypad for entering inputs into the FPGA chip and four 7-segment
displays for displaying outputs from the chip. The conceptual illustration of the
calculator is presented in Figure 1.
Calculator (FPGA) Calculator (FPGA) 44
. Figure 1: Calculator and its inputs/outputs
The 4x4 matrix keypad consists of 16 keys. Keys 0 to 9 on the keypad are used
for entering decimal digits, and keys A to F are used to set the different operations
as detailed in Table 1.
Table 1: Calculator key representations
Key Operation
A Calculator ON key, performs global reset (emulates power-ON function)
B Execute key, performs equal (=) operation
C Clear key, clears current result and reinitialises all registers of the calculator to 0
D Multiply key, performs multiplication on the two input operands
E Subtract key, performs subtraction on the two input operands
F Add key, performs addition on the two input operands
After the calculator is designed and implemented on the DE0 FPGA board, a user
should press key A, which mimics power-ON and initialises the calculator to a
known initial state. The same key can be used at any stage to mimic the powerON
operation. By pressing key A, all internal registers of the calculator are
initialised to zero (i.e. reset).
University of Auckland Lab 3 COMPSYS201 - 2020
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Calculator design spefifications
The user can then enter a positive decimal number of up to two digits (numbers
from 0 to 99) by pressing the number keys (0 to 9) one after another. Individual
digits are represented with their binary 4-bit codes (BCD). All entered numbers
are considered positive. The entered digits will be displayed on the 7-segment
displays, so the user knows which number was entered during this step.
The entered digits are internally stored in a shift register (Reg_A) that receives 4
bits (i.e. one decimal digit) at a time and always stores the last two entered digits;
all previously entered digits will be overwritten. These two digits represent the
first operand (operandA).
After entering the first operand, the user can press one of the operation keys: D
for multiplication, E for subtraction or F for addition operation. The 4-bit binary
code of the operation will be stored in the Reg_OP register.
After specifying the operation, the second operand (operandB) can be entered and
displayed on the 7-segment display in the same way as the first operand. This
operand will be stored internally in a shift register (Reg_B).
Once both operands and the operation are entered, the user can press key B to
perform the actual operation. The result is stored in a result register (Reg_R) and
displayed on the 7-segment display. If the user then wants to perform another
operation on a new set of operands, key C should be pressed to clear all internal
registers and 7-segment displays.
Based on these specifications, we can be certain that the range of input values are
from 0 to 99 and the range of output values are from 0 to 9801 (99x99), which
can be displayed on four 7-segment display. (Assuming that operandA is always
bigger than operandB, so no negative number will be produced as the output of
the calculator.)
To design this simple calculator, you can assume that you have the following
components made available to you:
1. Shift register: The provided shift register is 8-bit wide (i.e. can store two
4-bit digits). It has a reset and load_enable control input, and 4-bit data
input. When reset input is set to 1, the shift register content will be cleared
to zero. When load_enable input is 1, the number stored in the least
significant 4-bit will be transferred to the most significant 4-bit locations,
and the 4-bit input data will be stored into the least significant 4-bit
locations.
2. Register: The provided register is either 4-bit wide (for storing operation)
or 16-bit wide (for storing result). The register has load_enable control
input. When load_enable is 1, the input data will be stored in the register.
3. Arithmetic unit: The provided arithmetic unit can perform addition,
subtraction and multiplication according to a 4-bit binary code of the
operation, op_sel, where 1111 is for addition, 1110 is for subtraction, and
1101 is for multiplication.
4. Multiplexer: The provided multiplexer selects which number to be
displayed on the output interface (i.e. the 7-segment displays). The
University of Auckland Lab 3 COMPSYS201 - 2020
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multiplexer is a 16-bit wide 4-to-1 multiplexer with 2-bit control signal,
disp_sel, where 00 selects operandA for displaying, 01 selects operandB for
displaying, 10 selects result for displaying. You can assume unused I/O pins
are connected to 0s.
The calculator operations are defined by the following register transfer operations,
with their corresponding control signals in Table 2.
Table 2 Calculator register transfers and data flow
Control signal Register transfer Comment
clear Reg_A0, Reg_B0,
Reg_R0, Reg_OP0 Initialise all registers to 0
ld_a Reg_AKEY_IN Load operandA
disp_sel=00 DISPLAYReg_A Display operandA on 7-seg
ld_b Reg_BKEY_IN Load operandB
disp_sel=01 DISPLAY Reg_B Display operandB on 7-seg
ld_op Reg_OPKEY_IN Load operation
ld_r Reg_RReg_A op Reg_B Calculate and store result of the selected
operation (i.e. based on op_sel value)
disp_sel=10 DISPLAYReg_R Display result on 7-seg
Part 1: Design a datapath (1.5%)
Given the available datapath components, i.e. shift register, register, arithmetic
unit, and multiplexer. Design a datapath of the simple calculator as a block
diagram. The datapath is encircled by the dashed line in the figure (next page).
The datapath receives data input (i.e. numbers, operations, reset) from the
keypad and generates data output to the 7-segment displays (with the help of
interface hardware: the keypad driver and BCD to 7-segment decoder). Depending
on the pressed key, the following single bit control inputs are also generated for
the control unit FSM:
1. digit_in=1: Pressed key is a digit.
2. op_in=1: Pressed key is an operation (i.e. +, -, x).
3. execute_in=1: Key B (=) is pressed.
4. clear_in=1: Key C is pressed.
5. reset=1: Key A is pressed.
Task 1: Draw your datapath design as a block diagram (i.e. show each
internal component as a block), with clear indication of all necessary bus
connections, and control signals for each component. You don’t need to
worry about the internal bus width.
University of Auckland Lab 3 COMPSYS201 - 2020
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Control Unit FSM
o p_i n
ld_a ld_b ld_op
digit_i n
execute_i n
clear_i n
Four 4-bit
BCD to 7-seg
converters
Keypad driver
Keypad
Row
inputs
Column
outputs
ld_r disp_sel clear
Control signals
reset
2
4 4
Datapath
Value/Op
Data Input
Control inputs
Data
Output
Part 2: Design a control unit FSM (1.5%)
With the designed datapath, design a control unit FSM for it. The control unit is
responsible for coordinating the register transfer operations to achieve the overall
calculator function.
Figure 2 Control Unit Finite State Machine state transition diagram
For this calculator, we have designed an incomplete FSM state transition diagram,
as shown in Figure 2, where we have illustrated the conditions for the state
transitions according to the control inputs, but not the control signal outputs in
each state. The five states are:
initial operandA operation operandB result RREESSEETT oopp__ii
nn==11 ddii
ggii
tt__ii
nn==11 eexxeeccuuttee__ii
nn==11
ccll
eeaarr__ii
nn==11 digit_in=1, clear_in=1, execute_in=1 digit_in=1, clear_in=1, execute_in=1 op_in=1, clear_in=1, execute_in=1 op_in=1, clear_in=1, execute_in=1 digit_in=1, op_in=1, clear_in=1 digit_in=1, op_in=1, clear_in=1 digit_in=1, op_in=1, execute_in=1 digit_in=1, op_in=1, execute_in=1
University of Auckland Lab 3 COMPSYS201 - 2020
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• Initial - the calculator control unit FSM goes to the initial state either on
power-reset (which can happen from any state if Key A is pressed) or from
the result state after clear command (if Key C is pressed).
• operandA - in which the calculator receives, stores and displays operand
A.
• operation - in which the operation is received and stored.
• operandB - in which the calculator receives, stores and displays operand
B.
• result - in which the calculator executes the operation, stores and displays
the result, and waits to be reinitialised.
Task 2: Based on your datapath design, complete the table of control
signals provided below, by filling in the values of the control signals in each
state.
Control
signal
state
initial operandA operation operandB result
ld_a
ld_b
ld_op
ld_r
disp_sel
clear
Submit your datapath block diagram and the table of control
signals, as a PDF document on Canvas. The submission must
be made before 22nd May (Friday) 11:59pm to be considered
for marking.

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