RF and Microwave Engineering
Assignment
Part 1
Introduction
Passive microwave couplers are components that are required in a number of microwave
applications. Edge microstrip couplers provide broad bandwidths, however they are limited in terms
of the values of coupling that they can achieve.
This assignment is designed to let you demonstrate the following:
1. Your understanding of some basic principles of microwave passive circuit design.
2. Your ability to use an industry standard simulator (AWR) in designing simple microwave
passive couplers based on microstrip technology.
3. Your understanding of the limitations of this specific coupler technique.
Assignment Task
Edge Coupled Microstrip Coupler Design – Centre frequency = 3.5 GHz
You need to design two couplers, one with Coupling C=20dB and one with Coupling C=10dB
1. First design and simulate a coupler with ideal coupled transmission lines to verify your odd
and even mode calculations.
[20%]
2. Then implement the design in microstrip, using a substrate material chosen from Table 1.
Choose a substrate thickness (height) from the lists of available values in Table 1. The
minimum line widths and gap dimensions that can be etched on the microstrip board are
both 0.2 mm. Your line widths should be less than one quarter of a guided wavelength, to
avoid generating higher order modes on the line. Use TxLine in AWR iteratively to select the
optimum substrate thickness and the microstrip dimensions to achieve the required odd and
even mode impedances, within these constraints.
[30%]
3. Also include 50 ohm microstrip feed lines and bends or curves, arranged to make the
distance between the feed lines at the board edge at least 1.26 cm, to accommodate the RF
connectors. (But the connectors do not need to be included in the simulation.) Present a
layout window to view your circuit and check that everything looks sensible.
[20%]
4. Include rectangular graphs showing insertion loss, return loss, coupling and isolation of your
coupler, for both the ideal transmission line version and the microstrip version, over a
frequency range from 0.8fc to 1.2fc, where fc is your allocated centre frequency.
Add a polar plot showing the phase relationship between the direct and coupled port
outputs.
Verify that your designs achieve the expected results, in both amplitude and phase of the Sparameters
[30%]
2
Table 1
Dielectric
Constant
Dielectric
Loss Tangent
Available
Substrate
Heights, mm
Metal Metal
Thickness,
mm
Metal
Conductivity,
S/m
TLY-5 2.20 0.0009 0.09, 0.13, 0.25,
0.51, 0.79, 1.58,
2.36
Copper 0.035 5.88 x 107
RF-35 3.50 0.0018 0.25, 0.51, 0.76,
1.52
Copper 0.035 5.88 x 107
3
Part 2
High Gain Low Noise Amplifier Design
Introduction
Low noise amplifiers (LNAs) and power amplifiers (PAs) play an important role in the transmitter and
receiver of many wireless devices. Their performance can have a significant impact on the device’s
overall performance, in particular, the noise figure, gain and bandwidth.
Assignment Tasks
Literature Review
Read the paper “A Review of Technologies and Design Techniques of Millimeter-Wave Power
Amplifiers,” IEEE T. Microwave Theory Techn., vol. 68, no. 7, 2020. Write a brief summary of the
different solid-state technologies used to implement field-effect and bipolar transistors in the
millimetre-wave frequency band. In your summary, you should describe the challenges, advantages
and disadvantages of the different technologies. The summary should be less than one page.
[10%]
LNA Design
In this part of the assignment you are required to investigate the design of a two stage LNA with gain
greater than 20 dB and noise figure less than 2 dB. The investigation will focus on the noise figure,
return loss and stability of the circuit.
You should begin by creating the high-level schematic for the two stage LNA circuit shown in Fig. 1(a).
Note that the input, interstage and output matching networks should be implemented using simple Lsection
impedance matching networks using transmission lines. The LNA uses two Infineon BFP520
bipolar transistors, shown in the transistor sub-circuit in Fig. 1(b). The model for this transistor can be
found in the AWR elements browser under Circuit Elements -> Libraries -> AWR Website -> Parts by
Vendor -> Infineon -> Data -> RF Bipolar Transistors -> Low Noise Si Transistors up to 5 GHz -> BFP520.
Use the biasing conditions Vce = 1.0 V and Ic = 2.0 mA for the transistor. You do not need to include the
DC bias networks for the transistors in your design or layout.
(a) (b)
Figure 1 – (a) Top-level schematic for the two stage LNA. (b) Transistor sub-circuit without
stabilisation elements.
You are required to demonstrate a logical and sound engineering approach to your design process.
The following is the suggested approach; however, you may adopt an alternate approach provided it
is appropriately explained and justified.
4
1. Begin the design process by adding components to the transistor sub-circuit in Fig. 1(b) to
ensure that it is unconditionally stable. You may do this by adding some frequency dependent
resistance to the input or output of the transistor, or otherwise. Hint: plot the stability factor
K and supplemental stability factor B1 of the transistor sub-circuit to see which frequencies
are problematic, if any. Note that the stability analysis should cover all frequencies where
oscillations are possible.
[20%]
2. Now design L-section impedance matching networks using ideal transmission lines for both
the interstage and output matching networks shown in Fig. 1(a). These matching networks
should be optimised to maximise the gain of the two stage LNA (i.e. a conjugate impedance
match). However, some trade-off in gain may be required to keep the noise figure of the LNA
below 2 dB.
[40%]
3. Plot the overall performance metrics for the two stage LNA, including noise figure, gain and
return loss on a rectangular chart. You should also plot K and B1 to confirm unconditional
stability of your LNA design.
[15%]
4. Create a layout for the circuit using microstrip technology, choosing a suitable substrate
material. The additional loss of the microstrip will increase the noise figure of the LNA which
should be kept below 2.5 dB for the microstrip implementation. The layout will need to include
space for components to be soldered onto the circuit board. Include a copy of the layout in
your report.
[15%]
Report
You will need to create a report no more than 10 pages long for Part 1 and no more than 11 pages
long for Part 2, including figures and appendices. You should include a title page with your full name
and student ID number, as well as the module details. You should justify all your answers and
calculations, describe your methodology, and interpret and discuss all results. The report will be
assessed for clarity, completeness and correctness, using the criterion that a fellow engineer should
be able to use the report to either adopt or adapt your design.
The report shall be submitted to Canvas by the 25th March 2022. Late submission will be subject to a
5% per day marking penalty in accordance with University regulations.