# 辅导HW6讲解程序、辅导R编程语言

First, you need to build an inverter layout and schematic design by following the instructions in the

Choose a simple module for which you would like to do a full custom CMOS design.
1. Generate a hierarchical set of hand-drawn schematics (circuit diagrams) showing the CMOS
transistors in the lowest level (leaf) cells and the interconnection of cells at higher levels of the
hierarchy.
2. Layout each of the leaf cells using Cadence. Design rule check (DRC) each cell as it is completed.
Assemble and interconnect the cells hierarchically, consistent with your schematic hierarchy until
you have produced a physical layout of the entire module.
3. It is good practice to do a simulation of each cell in the hierarchy as you complete it. It is much better
to catch errors early in the design rather than waiting until you have the whole project assembled.
4. Simulate your design using the device models supplied in the tutorial to check for correct
functionality. Then determine how fast your design will run over a range of supply voltages and
temperatures. For example, simulate at VDD= 2.5V, 3.0V and 3.5V and at temperatures of -25C, 25C
and 100C.
5. Write a report that shows the circuit schematics and layout of each cell, DRC results, SPICE netlist
and simulation results. Describe the overall design process and make note of any difficulty you had
in getting the tools to work the way you expected.
6. You might choose one from the following design projects:
a) A ring oscillator consists of an odd number (5 or greater) of inverters connected in a loop.
Generate a layout of a ring oscillator using Cadence and perform a design rule check. Perform
simulation to measure the frequency of oscillation of your design. Use this result to determine the
value of t for this 180nm process. How does t change as a function of temperature and supply
voltage? How does the frequency of oscillation change as a function of load capacitance on the
output of the oscillator?
b) Use Cadence to create a layout of an 8-input NAND gate with NMOS transistors of width 8
(relative to the unit size) and PMOS transistors of width 2. Perform a DRC on your layout. Use
the following settings: width=8 NMOS and a width=2 PMOS.
MN1 D G S B NMOS L=0.18u W=3.2u
MP1 D G S B PMOS L=0.18u W=0.8u
Simulate your design to determine the rising and falling delays from each input to the output when
driving a very small output load (10 fF). How does this compare to what you would expect from
an Elmore delay analysis? (Since you don’t know the values of R and C for this process, you can’t
compare the absolute delay. But you can compare the relative changes as you go from one input
to another). Now change the output load capacitance to 1pF (much larger than the internal node
capacitances) to estimate the effective resistance R of a conducting unit sized NMOS transistor
for this process.

What you need to include in your report: