On-chip systems?
Laboratory work
Design of SoC
The task
1. Develop microprocessor SoC using Vivado IP-cores library. The SoC should contain:
1.1. MicroBlaze IP-core.
1.2. AXI GPIO IP-Core.
1.3. AXI Interconnect IP-core.
2. Develop the data processing algorithm for operation presented in the table below. The input
data should be defined in program code (internal arrays).
Matrix size Operation
8x8 C = (A-B)*(A+B)
3. Develop the implementation of hardware accelerator for the algorithm using synthesized C
programming language subset.
4. Integrate the hardware accelerator into developed microprocessor SoC. You need to connect
developed hardware accelerator using AXI4-Lite interface.
5. Develop the software for Microblaze IP-core that works with hardware accelerator. Your
program for Microblaze should contain two parts:
5.1. The part where the calculations were done by software only.
5.2. The part that works with hardware accelerator.
6. Develop the testbench that tests your SoC and gets the results of software and hardware
implemented calculations.
7. Compare the performance of software and hardware implementations of calculations.
8. Perform synthesis of the SoC and analyze the FPGA utilization.
Tools
Xilinx Vivado 2019.1
Xilinx Vivado HLS 2019.1
Xilinx SDK 2019.1
Target platform: Nexys A7 development board (FPGA XC7A100T-1CSG324C).
The content of the report
1. The student name and HDU ID
2. The picture of the SoC with hardware accelerator
3. Register map of your hardware accelerator. Please present Register Map in table view.
4. The time of algorithm execution for software only implementation and using hardware
accelerator.
5. The set of timing diagram with simulation results. You need to show the moments with
the time of calculation with software only implementation and using hardware
accelerator.
6. The source code of the program for Microblaze IP-core
7. The source code of:
1. The implementation of used hardware accelerator
2. The test-bench
The report you need submit using this form: