ECE 4514: Digital Design II Spring 2023
This course is devoted to advanced digital design techniques for developing complex digital circuits. It emphasizes system-level concepts and high-level design representations that also meet particular design constraints such as performance, power, and area. The methods presented will be appropriate for use with automated synthesis systems. You will gain greater experience with using commercial hardware description language simulation and synthesis tools to design a series of increasingly complex digital systems, and with using Field Programmable Gate Arrays (FPGAs) to implement those systems.
All of the material that you learned in ECE 2544 and 3544 is an important foundation. In particular, we assume you are coming into this class already familiar with the Verilog HDL, Boolean algebra, logic gates, Karnaugh maps, flip-flops, combinational functional blocks (multiplexers, decoders, encoders, and so forth) Mealy and Moore finite state machines, state diagrams and tables, state assignment, synchronous sequential functional blocks(registers, counters, RAM and ROM, and so forth) and asynchronous devices. A grade of C- or better in ECE 3544 is required in order for you to enroll in ECE 4514. The department will enforce this prerequisite requirement.
Advanced digital design techniques for developing complex digital circuits. Emphasis on system-level concepts and high-level design representations while meeting design constraints such as performance, power, and area. Methods presented that are appropriate for use with automated synthesis systems. Commercial hardware description language simulation and synthesis tools used for designing a series of increasingly complex digital systems, and implementing those systems using Field Programmable Gate Arrays (FPGAs). Pre: 3544. (3H, 3L, 4C).
You will be using the DE1-SoC kit by Terasic. This is the same board that you used in ECE 3544. The board will be distributed in class at the start of the semester and collected in class at the end of the semester. If you do not return your board, you will not receive a grade in the class.
You will be using Intel’s Quartus Prime Lite design software. Version 20.1.1 will be used rather than the later versions that require a license for the Questa simulator. The tools can run either on a Windows or Linux host. A VM is best avoided because of potential issues with the USB cable driver for communication between your laptop and the DE1-SoC board.
Rather than use a text which can quickly go out of date with an evolving HDVL, ChipVerify provides an excellent SV language reference with lots of examples. FPGAcademy has valuable tutorials targeting the board and tools used in this course. Quartus Prime Lite includes online help and user forums.
Having successfully completed this course, the student will be able to:
Apply advanced design strategies that include testing and debugging techniques;
Meet specified design constraints, such as performance, power, and area, using contemporary techniques;
Use multiple clocks and asynchronous system techniques for high-speed data transfer;
Catalog Description:
Required Materials:
Learning Objectives:
Grading:
hardware technologies.
In-class quizzes
Homework
Projects
Interview-like problem solving 1 Interview-like problem solving 2
10% 15% 50%
(Tuesday Feb 28th in class) 10% (Tuesday April 4th in class) 15%
4. Prototype complex digital systems that meet specific design constraints;
5. Compare and contrast the relative capabilities of various contemporary digital
Grading policies:
“In-class quizzes” will take place randomly through the semester. The lowest few scores will be dropped so don’t worry about missing one. These quizzes serve to confirm that you attended a class and were paying attention to what was covered in the class.
Homework will serve to reinforce topics.
Roughly 5 projects will be assigned and they may build upon each other. Procrastination will be a good way to receive low scores on projects.
“Interview-like problem solving” will be similar to the type of question that you get asked when applying for a digital hardware verification / design job. I did this many times to screen applicants at Xilinx and developed a large collection of problems that can be solved in about an hour. The first session will focus on verification and the second will focus on design. Most digital hardware design consists of a state machine controlling a datapath; applicants who did not know that or do that where appropriate were quickly eliminated.
Letter grades are assigned according to the following table without rounding:
Minimum Letter Numeric Grade Grade
0F 61 D- 64 D 67 D+ 70 C- 74 C 77 C+ 80 B- 84 B 87 B+ 90 A- 94 A
Final semester grades will be determined after all work is completed and graded. The same grading scale will always be applied to all students. There is no grade curving to produce specific proportions of letter grades; in other words everyone could conceivably receive a grade of A. Students with questions about their performance should discuss them with the instructor.
All assignments and projects are due when specified unless there is something beyond the control of the student such as illness or a personal / family emergency. You need to contact the Dean of Students if something occurs beyond your control. Procrastination (“my Internet went down at 11:59 pm”) is not considered beyond your control even if it is habitual. Work that is not turned in will receive a grade of zero.
Course Schedule: Honor Code:
If you feel that an error has been made in the grading of an assignment or an exam, you must present the work to the GTA (if the GTA graded the work) or your instructor (if your instructor graded the work) within one week after the graded work is made available to you. Virtual office hours are a good time to address these issues rather than before/after class when we do not have access to the grade list or proper time to consider the matter. Grades will not be changed after the one week period. Appeals should address specific grading errors.
The assignment schedule is maintained on Canvas.
Honesty in your academic work develops into professional integrity. As such, the Honor Code will be strictly enforced in this course. All aspects of your course work are covered by the Honor System. All examinations and assignments are expected to be your own individual work. You must not claim credit for work you did not perform. We will use plagiarism detection tools which cannot be thwarted by superficial changes such as changing variable names or reformatting. Report any suspected violations of the Honor Code promptly. Discussion and cooperative learning on general topics covered in the course using a tool such as Piazza is encouraged. However revealing your solution code to other students when posting a question on Piazza must be avoided since it is an Honor Code violation.
The Undergraduate Honor Code pledge that each member of the university community agrees to abide by states:
“As a Hokie, I will conduct myself with honor and integrity at all times. I will not lie, cheat, or steal, nor will I accept the actions of those who do.”
Students enrolled in this course are responsible for abiding by the Honor Code. A student who has doubts about how the Honor Code applies to any assignment is responsible for obtaining specific guidance from the course instructor before submitting the assignment for evaluation. Ignorance of the rules does not exclude any member of the University community from the requirements and expectations of the Honor Code.
Commission of any of the following acts shall constitute academic misconduct. This listing is not, however, exclusive of other acts that may reasonably be said to constitute academic misconduct.
CHEATING: Cheating includes the intentional use of unauthorized materials, information, notes, study aids or other devices or materials in any academic exercise, or attempts thereof.
PLAGIARISM: Plagiarism includes the copying of the language, structure, programming, computer code, ideas, and/or thoughts of another and passing off the same as one's own original work, or attempts thereof.
FALSIFICATION: Falsification includes the statement of any untruth, either verbally or in writing, with respect to any element of one's academic work, or attempts thereof.
FABRICATION: Fabrication includes making up data and results, and recording or reporting them, or submitting fabricated documents, or attempts thereof.
MULTIPLE SUBMISSION: Multiple submission involves the submission for credit – without authorization from the instructor
receiving the work – of substantial portions of any work (including oral reports) previously submitted for credit at any academic institution of attempts thereof.
COMPLICITY: Complicity includes intentionally helping another to engage in an act of academic misconduct, or attempts thereof.
VIOLATION OF UNIVERSITY, COLLEGE, DEPARTMENTAL, PROGRAM, COURSE, OR FACULTY RULES: The violation of any University, College, Departmental, Program, Course, or Faculty Rules relating to academic matters that may lead to an unfair academic advantage by the student violating the rule(s).
Clarification is provided for each definition with some examples of prohibited behaviors in the Undergraduate Honor Code Manual.
If you have questions or are unclear about what constitutes academic misconduct on an assignment, please speak with your instructor. We take the honor code very seriously in the course. The normal sanction we will recommend for a violation of the Honor Code is an F* sanction as your final course grade. The F represents failure in the course. The “*” is intended to identify a student who has failed to uphold the values of academic integrity at Virginia Tech. A student who receives a sanction of F* as their final course grade shall have it documented on their transcript with the notation “FAILURE DUE TO ACADEMIC HONOR CODE VIOLATION.” You would be required to complete an education program administered by the Honor System in order to have the “*” and notation “FAILURE DUE TO ACADEMIC HONOR CODE VIOLATION” removed from your transcript. The “F” however would be permanently on your transcript.
For additional information about the Honor Code, please visit
https://www.honorsystem.vt.edu/
Any student with special needs or circumstances should feel free to meet with or otherwise contact your instructor.
Special Needs:
Disability Accommodation: The following is the Virginia Tech syllabus statement from the VT SSD office:
Religious accommodation:
Virginia Tech welcomes students with disabilities into the University’s educational programs. The University promotes efforts to provide equal access and a culture of inclusion without altering the essential elements of coursework. If you anticipate or experience academic barriers that may be due to disability, including but not limited to ADHD, chronic or temporary medical conditions, deaf or hard of hearing, learning disability, mental health, or vision impairment, please contact the Services for Students with Disabilities (SSD) office (540-231-3788, ssd@vt.edu, or visit www.ssd.vt.edu). If you have an SSD accommodation letter, please meet with me privately during office hours as early in the semester as possible to deliver your letter and discuss your accommodations. You must give me reasonable notice to implement your accommodations, which is generally 5 business days and 10 business days for final exams.
If participation in some part of this class conflicts with your observation of specific religious holidays during the semester, please contact your instructor during the first two weeks of class to make alternative arrangements.
Accommodations for medical or personal/family emergencies: If you experience a personal, medical, or family emergency that necessitates missing class or being unable to participate 4
in coursework, then please contact the Dean of Students. They will get the necessary information from you and can arrange to notify all of your professors regarding the time that you will be unable to participate in the course.