CptS260: Introduction to Computer Architecture
School of Electrical and Computer Engineering
Assignment 7: Pipelined MIPS Execution on Pipelined a CPU (5%)
Assignment Description
In class we have gone over examples of how a pipelined MIPS CPU will execute instrucitons.
We will assume there is not a delay slot for a branch instruciton. For this assignment you will apply knowledge learned to analyze a program by hand when they are executed by a pipelined MIPS CPU. The code fragment is given below. We will analyze the portion of codes in red only.
# sum the elements of an array of 100 elements
# use an address label instead of fixed address
# initialize the array with 1 to 100 using index
# use addi a negative number for subtraction
# simulate online at - http://www.csbio.unc.edu/mcmillan/miniMIPS.html
# S. L. Lu 1/12/2024
.data
array:
.space 400
.text
main:
addi $t0, $zero, 100 # init index i ($t0 or $8) with 100
la $s0, array # load data addr into $s0
init: # initialize array with 100 down to 1
sw $t0, 0($s0) # store array[i] into ($s0 or $16)
addi $t0, $t0, -1 # decrement index by 1
addi $s0, $s0, 4 # inc addr by 4 since 32b is 4B
bne $t0, $zero, init # test if i is 0; if not go to init
# start of array_sum, $s0 has array+400
addi $t0, $zero, 100 # reset index to 100
addi $s2, $zero, 0 # sum = 0 (sum is in $s2 or $18)
loop: # sum array backward
addi $s0, $s0, -4 # next array element (go backward)
lw $s1, 0($s0) # load array[i] in $s1
add $s2, $s2, $s1 # sum = sum + $s1
addi $t0, $t0, -1 # decrement index by 1
bne $t0, $zero, loop # test if index is 0; if not loop
done: # result in $s2 ($18) = 13BA(h) 5050(10))
(1) Assume the 5-stage pipeline machine’s register port cannot support read and write at the same time. Assume there is no implicit bypass forwarding of execution result to register read. Further assume there is only 1 memory unit which does not allow read and write the memory at the same time. What is the average CPI for executing this code segment. (20 pts)
(2) Assume the 5-stage pipeline machine support 2-read ports and 1 write-port. Assume there is no implicit bypass forwarding of execution result to register read. Further assume there is only 1 memory unit which does not allow read and write the memory at the same time. What is the average CPI for executing this code segment. (20 pts)
(3) Assume the 5-stage pipeline machine support 2-read ports and 1 write-port. Assume there is no implicit bypass forwarding of execution result to register read. However, the memory has two ports which allows reading and writing of memory at the same time (or there are instruction cache and data cache). What is the average CPI for executing this code segment. (20 pts)
(4) Assume the 5-stage pipeline machine support 2-read ports and 1 write-port. There is implicit bypass forwarding of execution result to register read and the memory has two ports which allows reading and writing of memory at the same time (or there are instruction cache and data cache). What is the average CPI for executing this code segment. (20 pts)
For each of the above tasks you need to use Microsoft Excel to show the pipeline stages as given in lectures.
(5) Assume the above code is executed on the processor as described in (4) with a 2 GHz clock frequency. What is the execution time in nanoseconds? Is there a way to rewrite the code to improve the overall performance (with less execution time)? (20 pts)
(6) Turn in your pipeline pictures for each tasks described above together with answers to questions in (5).