ALU and RAM
COMP 273 Assignment 2 - Fall 2024
Available: 19 September 2024 - Due date: 08 October 2024
Submission Instructions
All work must be your own, and must be submitted by MyCourses. You are allowed to submit as many times as you want before the deadline. Include your name and student number at the top of your Lo- gisim circuit file. Your circuits should be submitted as .circ files, must have the circuit name (ALU.circ or RAM.circ), and respect the circuit layout (sub-circuit appearance, viewed with the right-most toolbar but- ton in Logisim) to make it easier for TAs to test. Include a readme.txt file with any special instructions, or comments on limitations of your solutions. Submit the 3 requested files only (2 .CIRC files and readme.txt file if needed), and do not create an archive (do not submit a zip file). Be sure to check your submission by downloading your submission from the server and verifying that it was correctly submitted. You will not receive marks for work that is incorrectly submitted.
Late submissions are allowed up to 3 days after the due date with 10% penalty (in case penalty waiver is not requested or already used for A1).
Purpose
• Learning about the basic circuitry in ALU and RAM.
• To get used to using sequential circuits such as flip-flops and registers.
• Using clock to control circuit execution.
• To get used to using status flags in ALU.
• To get used to using RAM addresses.
• To get used to splitting and merging signals.
1 ALU (20 marks)
Use Logisim to implement a nibble ALU, i.e. 4-Bit ALU following the design of ALU seen in class. The ALU circuit has the following inputs and outputs as shown in the following figure:
• Inputs: A and B (nibble sized register, 4 bits each) which represent the two operands to bemanip- ulatedby the ALU circuit, 1-Bit A invert mode, 1-Bit B invert Mode, and 2-bit operation mode.
• Outputs: Result (nibble sized register, 4 bits) and Status register (3 bits). The Status register bits are updated by the result stored in result register as following: Bit 0 (LSB) = sign, Bit 1 is zero, and bit 2 (MSB) is sign overflow. Please note that the sign bit should indicate if the result of arithmetic operations (i.e., add or subtract) is positive (sign bit =0) or negative (sign bit = 1). Thus, sign overflow flag should betaken into consideration in the circuitry used to set sign flag. See the following example:
-710 - 610 = 10012 − 01102 = 10012 + 10102 = 00112 , with sign overflow bit = 1 In this case, the sign bit should be 1 as the results of −710 - 610 is negative.
• The operation of ALU should follow the table shown at the right side of the above figure. This quite similar to the one seen in class except that we kick out the ”SLT” operation from the scope of this ALU circuitary.
• You must build the circuit from the following components ONLY: Pins, probes, wires, registers, flip-flops, clock, AND, OR, NOT, and XOR. You CANNOT use any prebuilt adder circuits, or any other prebuild items from Logisim. Optionally you can use: tunneling and “adding a circuit” from the project menu.
• Your final circuit must use designs we covered during class. You cannot use any outside (other sourced) circuit designs.
• Add a clock to control the execution of this circuit. You are allowed up to 2 clock cycles to execute a single ALU operation.
Execution
Your ALU circuit must be able to do the aforementioned operations for any input numbers that fit within a singed nibble. Note that The TA will input the numbers into the A and B pins in 2’s complement form. by hand. For example, to test 1- (-1), A is set to 0001 and B is set to 1111, and the ALU should perform. the ”SUB” operation.
Marking
Circuit must execute to be graded.
• +9 Circuitry for ALU operations: +6 Add/SUB circuitry, +1 for each circuitry for AND, OR and NOR operations.
• +6 Status determination circuits: +3 sign overflow bit, +2 sign bit, and +1 Zero bit.
• +5 Registers.
• -3 points for not following instructions.
• -5 points for not using the clock.
2 RAM (20 marks)
Implement 4 nibbleRAM,i.e. RAM with 4 locations and each location is 4 bits wide following the design of RAM seen in class. The RAM circuit has the following inputs: A mode bit, 2-bit address, and 4-bit data input, and has 4-bit output as shown in the following figure
• Mode, Address, Data input, and Data output are registers. However, you are required to create these registers from scratch using flip-flops. Do not use the Logisim Register pre-built unit. You can pick any flip-flop you want. Group and synchronize the flip-flops for one register as a single unit. As seen in class.
• Similarly, Row 0 to Row 3, the four nibbles of RAM, are registers. Also create them from scratch using any flip-flop you want. Do not use the Logisim Byte pre-built register unit or any pre-built unit. Group and synchronize them into units.
• Add a clock to control the execution of this circuit. You are allowed up to 2 clock cycles to execute a single RAM operation; a read or write.
• You CANNOT use any prebuilt/automatic circuits. Optionally you can use: tunneling and “adding a circuit” from the project menu.
Execution
The RAM circuit should be able to perfrom the following:
1. Given a specific address and data input value with Mode 0 for Write, the data value should be saved into the RAM nibble once the clock is on.
2. Given a specific address and Mode 1 for Read, the content of the specified nibble should be loaded into Data output once the clock is on.
3. The previous process could be repeated as often as we want. Data previously stored in the nibbles should still be present unless they are overwritten.
Marking
Circuit must execute to be graded
• +1 Mode register.
• +2 Address register.
• +3 Data input and data output registers.
• +3 Addressing circuitry.
• +2 4 nibbles of RAM.
• +3 Write operation.
• +3 Read operation.
• +3 Repeatable infinitely.
• -3 points for not following instructions.
• -5 points for not using the clock.