ELEC4602
Microelectronics
Design and Technology
Lab 1: Layout
Objective
The objective of this laboratory session is to give initial exposure to the software environment that will be used in this course throughout the semester, and to introduce integrated circuit layout. We will be using the industry standard integrated circuits design system, Cadence, which includes a complete set of tools for IC design. Cadence run under a Linux environment, and have extensive on-line documentation.
The process we are going to use in this course is the NCSU 45nm FreePDK45 CMOS process; see the course web page (note that the Design Rules only allow you to draw transistors as short as 50nm; also note that dimensions used in Cadence is µm).
Computer laboratory access
Cadence run under the Linux operating system, which run as a Virtual Machine (VM) under Windows on PCs in both the EE-108 signal processing laboratory and in rooms EE-202/EE-217 as well as in the open space area EE-209. First log-in to the Windows system with your z-pass. Then, to start the VM, double-click on the Cadence icon on the Windows desktop (it will take a little while for the VM to boot); you may want to maximize the VM window and un-pin the VM toolbar. No log-ins are required in starting the VM, but all data will be erased upon log-out, so make sure you save your work: first close down Cadence, then copy the cadence work directory to a USB key or a cloud storage; next time you start, first copy the cadence work directory from your USB key / cloud storage to the design computer’s home directory (desktop),then start Cadence. This order is important.
Using the Cadence IC design tools
Log on to the design computer and open a shell (command line) by right clicking on the canvas and choosing Open Terminal on the menu. Then set-up the FreePDK design environment and start the Cadence Virtuoso IC design tool from the cadence work directory:
[eleccds@localhost ˜]$ FreePDK
FreePDK45 process - setup ready
[eleccds@localhost cadence]$ virtuoso -64 &
You can close the Library Manager window if you wannt. Note that Cadence is a very compli- cated piece of software of which you will be exposed to only a tiny fraction; the lab instructions attempt to guide you through with a minimum of effort on your side, so please follow the in- structions accurately. (For example, if you were to copy your work to the USB before quitting Cadence, you will copy a lock-file that will prevent you from editing your work in your next session; the lock-file can actually be safely removed, but it is preferable not to end up in this sit- uation). Once you are more familiar with the software, you are expected to explore it by yourself throughout the labs.
Creating a design library
First time (only!) you start Cadence, you will need to create a design library that you will use for the course: Select File-New-Library . . . from the menu in the Virtuoso - log window, put in a library name, e.g. lib4602, and select Attach to an existing techology library; then click OK. In the new window, for the Technology Library choose
NSCU TechLib FreePDK45
and click OK.
Creating a cellview
Now you need to create a design cell; for this lab it need to be a layout type cell: select from the menu File-New-Cellview . . ., and choose your new library (lib4602) as Library, key in a Cell Name, e.g. nand4602, and select layout as the Type (that should fill in layout in View field and Layout L in the Open with field); click OK. A window Next License may pop up asking if you want to the 95310 license instead of the 95300 license - click yes. Now, the Virtuoso layout editor should open, ready for editing the layout of your new cell.
Doing layout
In this lab, the task is to lay out the CMOS nand gate shown in figure 1; transistor sizes are shown in the figure. Remember to save your design frequently: select File-Save to save.
Figure 1: CMOS nand gate (a),transistor dimensions (b), basic MOS layout (c)
Adding a rectangle: click on a layer (e.g. poly) in the layer palette, making sure you select the drw (as opposed to the net) version of the layer; then in the Virtuoso window, select the menu item Create-Shape-Rectangle, click on the desired position for the first corner of your rectagle, move the mouse and click on the oposing corner to finish the rectangle. Continue, thus, adding rectangles in different layers to build up devices and interconnects. You need to adhere to the design rules, see
https://eda.ncsu.edu/freepdk/freepdk45/
or the course website (note again that Cadence list all dimensions in µm, not in nm). Relevant layers are:
pwell; nwell; vtg; active; nimplant; pimplant; poly; contact; metal1; via1; metal2
Note: in the FreePDK45 process, NMOS transistors must be placed within a pwell and PMOS transistors must be placed within an nwell; all transistors must be within a threshol voltage select layer – for N VTG/P VTG transistors this select layer is vtg; nimplant/pimplant is sometimes called nselect/pselect.
Adding a path: for interconnects, the wire (path) tool is very convenient; click on the layer in the layer palette in which you want the wire; choose the menu item Create-Wiring-Wire; click on the starting point and each time you want a bend; double click to end. Note: it makes no difference to the circuit whether shapes are created as wires, polygons or rectangles.
Moving objects: select Edit-Move in the menu, click on an object, move it, and click again, where you want to drop it.
Resizing objects: select Edit-Stretch in the menu, click on an object edge, resize the object, and click again to finalise.
Rulers: you can measure distances on the layout by selecting Tools-Create Measurement and click start-point and end-point in the layout; you should place rulers showing key dimensions in your layout for this lab exercise.
Bulk connections: remember that every n-well need to have a connection (using an n+ junc- tion; i.e. active with nimplant) to VDD with regular intervals and every p-well need to have connections (using a p+ junction; i.e. active with pimplant) to Ground with regular intervals (maybe one per one or two transistors; these are the transistor bulk connections).
Contacts: place whenever the junction size allows it; use contacts liberally!
Ports: ports (or “pins”) are used to indicate to where in the layout cell connections should be made when instantiating the cell; these must correspond to ports in the cell schematic; ports should be placed in metal layers. To place a port, first select the net version of the layout layer in which the connection must be made (e.g. metal1), then choose Create-Pin . . . and in the pop-up window fill in the port name (no spaces, e.g. inputA) in the Terminal Names field; choose the appropriate I/O Type and Signal Type as well. Then draw the port on the layout; the drawn port rectangle must sit inside the drw layout shape of the connection layer. All cell inputs, output and supplies must have ports. Port rectangles must must have a label placed inside them:
Labels: you need to label all devices and nodes in your layout. To add a label, choose Create- Label . . . in the menu; then enter the label name (no spaces!), e.g. nodeX, in the Label (Pattern) field of the pop-up window, and choose the layer (probably the net version layer or the layer in which the node resides, such as metal1); finally click on the layout where you want the label to go.
Design rules checking
Once the layout is done (or indeed, as it progresses) it need to be verified against the Design Rules. To check your design, select Calibre-Run nmDRC . . . in the menu. The settings in the Calibre nmDRC window popping up should be correct – click Run DRC (you can allow the tool to overwrite the temporary files it generates). All Design Rule tests will show up on in another Calibre window popping up; a green tick means the rule check has passed while a red cross means there is at least one violation of that design rule – click on a violated rule and then on one of the numbers in the list of individual violations to see what the rule violation is; double-clicking on the numbers will show where in the layout the violations are in the Virtuoso layout window. Make sure to take a screen-shot of both the beginning and the and of the DRC Summary Report as documentation for your report.
Exporting images
To export images of your layout for your report or other documentation, choose File-Export Image. . . in the Virtuoso layout window menu. In the Export Image pop-up window, you can control image capture, scaling, coulours, file formats, etc., to your liking. White or transparent background images works best for reports; for better image quality set Scale exported region by: to 2 .00x. Enter your target filename in the Name field and click Save to File. Note, ex- porting images yields much better graphics that screen captures; rulers, unfortunately do not appear on the expoted image, so you will have to use screen-shots to capture these.
Report
A short report in .pdf format on the laboratory exercise must be prepared and uploaded on the course Moodle site no later than the due date. This need to include:
• Your layout of thenand gate; on this layout:
– label all transistors,
– label all nodes, and
– place rulers showing key dimensions of your layout.
• a layer guide making it possible to clearly identify the layers in your layout.
• Screen-shot of DRC result.
Saving your data
The account will be cleared out when you log out — so remember to bring a USB thumb-drive to store your data on: make sure that you quit Cadence first, or you will not be easily be able to edit your design; then insert a USB key, copy the cadence directory to this, and finally unmount (or eject) the key before removing it from the computer. When you want to use cadence again, make sure that you fist copy the cadence directory from the USB key back to the computer before you start Cadence. Alternatively you can use a cloud storage; the procedure is similar.
General computer laboratory access
Computers in the Electrical Engineering building (in EE-202, EE-209 and EE-217) are equipped with the Cadence design tools. To access these after hours, you can login there using your normal account credentials ( z1234567, etc.), and start the VM Linux session as described above. As for the EE-108 laboratory, the account is cleared after you log out.