Department of Electrical Engineering
Final Examination
EE E4321. Fall, 2019
December 16, 2019
Time: 180 minutes
Total: 250 points
1. Consider an inverter operating with a supply voltage of VDD with logic signals that swing between ground and VDD. Let VT = 0.32 V for the nFET and -0.32 V for the pFET. Let the above-threshold drain current be governed by the equation ID=WCoxvsat(VGS-VT), where WCoxvsat = 1 mA/V, for the nFET and by the equation ID=WCoxvsat(VSG+VT), where WCoxvsat = 1 mA/V, for the pFET. For the nFET, Ioff is defined by VGS= 0.0 V and VDS = VDD. For the pFET, Ioff is defined by VSG = 0.0 V and VSD = VDD. For the nFET, Ion is defined by VGS=VDD and VDS=VDD. For the pFET, Ion is defined by VSG = VDD and VSD = VDD.
(a) Let VDD = 1.2 V. If the current of the nFET (pFET) is 100 μA at VDS (VSD) of VDD at a VGS (VSG) of 0.32 V, what is the off-current (Ioff)? Assume a subthreshold slope of 90 mV/decade and ignore DIBL. What is the Ion/Ioff ratio for each transistor? (10 points)
(b) Now let VDD = 0.2 V. What is the Ion/Ioff ratio for each transistor? (10 points)
(c) If this inverter drives a load of 10 fF, estimate the delay of this inverter at VDD = 0.2 V. (10 points)
(d) If the inverter (with VDD = 0.2 V) is stimulated with a 50%-duty-cycle square wave at its input switching between 0 and 0.2 V with a period of 1 nsec, what is the average power consumed by this inverter? (10 points)
2. Consider short-channel effects. Remember that device VT is strongly affected by bulk
charge under the channel.
(a) One typically finds that the magnitude of the threshold voltage of a short-channel device decreases with increasing VDS. Why is this? (10 points)
(b) Before the advent of advanced halo doping techniques, one found that circuits with smaller channel lengths had threshold voltage of lower magnitude. Why was this? This is the effect we described in class as “VT rolloff.” (10 points)
(c) Modern device technologies have introduced halo doping. In this case, the region
directly under the source and drain is more heavily doped than the substrate as a whole. This helps control the extent of the source and drain depletion regions. The case of the nFET is shown below. In the presence of halo doping, one generally finds an “inverse” rolloff in which smaller channel lengths lead to higher magnitude threshold voltages. Why might this be? (10 points)
3. Consider the carry chain of the four-bit static ripple carry adder shown below. Cload models the loading of the sum circuit at each bit. For this technology, transistors are assumed to provide kgate = 1 fF/μm of loading. Assume that the fanout-of-one (FO1) delay for this technology is τ1 = 25 psec.
(a) If W = 1 μm, what is the delay of the carry chain from Cin to Cout? (10 points)
(b) If VDD = 1.2 V and W = 1 μm, what is the energy dissipated by a single propagated transition through the carry chain? (10 points)
(c) What value of W will minimize the delay of this carry chain? What energy will be dissipated at this value of W for a single transition through the chain? (9 points)
(d) Repeat the calculation of (c) if Cload = 0. (10 points)
4. Sketch the waveforms for scan_enable, clock, scan_in, and scan_out for a test sequence to scan in a test pattern, clock the system once, and scan out the resulting pattern such that a stuck-at-one fault at node X could be detected. Show where this would be detected in your waveform. (20 points)
5. Consider the clock chopper circuit shown below. The delay block (labelled ∆) can be implemented with an even number of inverters.
(a) Consider two clock-chopped flip-flops separated by combinational logic as shown below. Assuming that the combinational logic represents a fixed delay of 200 psec and there is skew between CLK1 and CLK2 such that CLK2 arrives 100 psec earlier than CLK1, what is the maximum value ∆ (the pulse width of the chopped clock) can have and still ensure correct functionality? Assume that the latches have a hold time of 50 psec on their closed clock edge. (10 points)
(b) Assume that this chopped clock with the pulse width calculated in (a) is driven from an inverter with a load capacitance of 200 fF. The inverter is sized 4 μm / 2 μm in a technology with a FO1 delay of τ1 = 25 psec. Assume a gate capacitance of 2 fF/μm. Sketch the waveform. of the clock as received by the latch. What will be the “height” of the pulse? What problems might this present? (12 points)
6. Consider the following dynamic PLA structure.
(a) We discussed in class how it is necessary to derive the clocks φAND and φOR in such a manner that the OR plane does not being to evaluate until after the AND plane has evaluated. Furthermore, both φAND and φOR must allow for adequate precharge time. If the clocks satisfy this relationship, what is the logic function of this PLA (i. e, what are y0 and y1 as a function of x0, x1, and x2)? (10 points)
(b) Design a replica AND row, two instance of which can be used in the circuits below to generate φAND and φOR to meet the timing constraints described in (a). (8 points)
7. Consider a long global wire from driver A to receivers B and C as shown below. Assume that the wire is 0.4 mm wide and has a resistance of 0.076 O/square. Its capacitance per unit length is given by:
Assume that each receiver has a load of 100 fF.
(a) Explain why the capacitance has the functional form specified above. (8 points)
(b) Calculate the Elmore delay from A to B. (10 points)
(c) Assume the Elmore delay calculated in (b). If the FO1 delay of this technology is 50 psec, would resistance have to be considered for this line in calculating the delay from A to B? Explain. (8 points)
(d) Now imagine widening the wire from A to X from 0.4 μm to 10 μm. What is the Elmore delay now from A to B? (10 points)
8. Consider the following path from a dynamic gate through two static gates. Assume that the technology is characterized by a gate capacitance per unit width of 1 fF/μm. Let the FO1 delay of this technology be τ1 = 25 psec.
(a) Estimate the delay form A rising to E rising in the evaluate phase (φ = 1) if W1=W2=W3=W4=W5=W6= 1 μm. Let Csidebranch = 0. (10 points)
(b) Keeping W1 fixed at 1 μm, resize the network to minimize the delay from A rising to E rising with Csidebranch = 0. Please do not allow the beta ratio (ratio of pFET strength to nFET strength) for any gate become more than 4 or less than 0.25. (15 points)
(c) Using the sizing of (b), what is the delay from A rising to E rising with Csidebranch = 200 fF. (10 points)
9. Joe Engineer is designing a simple pass-transistor latch as shown below.
He finds that he is unable to write the latch; that is, when clk is high, Y is not affected by the value of A. What has gone wrong? How can this be fixed? (10 points)