CS/EE UY 2204: Digital Logic & State Machine Design
Course/Lab Assistants:
The course assistants will assist in both the theory and lab components of this class. Their office hours will coincide with the lab hours below, so if you would like to ask a question please ask during their lab hours. You are welcome to use Brightspace forums for questions also.
(FPGA) Lab Manager:
● Chris Ng ([email protected]); Contact person for all IT issues and lab access.
Course Textbook:
● Fundamentals of Digital Design (With Verilog), Third Edition, Brown and Vranesic. (Please look under Resources on NYU Classes)
Optional Reference Book: (Free e-version can be downloaded from NYU Library):
Grading:
● Homeworks: 10% (Self-Graded. Note that we will be randomly checking a subset of submitted HW solutions.)
● Labs: 30%, in teams of 2 (Remote: We will be providing log in information to the lab, RH227. Students can also go into the lab during assigned Lab sections if they prefer)
● Midterm: 25%
● Final: 35%
Tentative Class Schedule
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Week #
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Lecture Contents
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Labs/HWs
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Notes
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Jan 22
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Introduction: Digital Hardware, Digital Representations; Boolean Logic Functions
1.1-1.5; 2.1-2.4
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You do not need to attend Labs this week, since Lab 1 will only be assigned on Fri.
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Jan 29
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Boolean Algebra and Intro to Verilog
2.5-2.10
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Mon: Lab 1 Assigned
Mon: HW 1 Assigned
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Feb 3,5
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Minimizing Boolean functions
2.11-2.16
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Fri: Lab 1 Due
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Feb 10,12
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Number Representation and Arithmetic Circuits
3.1-3.3; 3.5-3.6
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Wed: Lab 2 Assigned (Fabricate your own chip!)
Mon: HW 2 Assigned
Fri: HW1 Due
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Feb 17,19
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Combination Circuit Building Blocks
4.1-4.5
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Thurs: Lab 2 Due
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No class on Feb 19th (President’s Day)
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Feb 24,26
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Verilog for Combination Circuits
4.6
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Fri: HW 2 Due
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Mar 3,5
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Sequential Circuit Building Blocks
5.1-5.4; 5.8-5.9
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Mon: Lab 3 Assigned
Wed: HW3 Assigned
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Mar 10,12
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Implementation Issues + Verilog Implementation
5.10, 5.13-5.17
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Mar 17,19
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Mon: Lab 3 Due, Lab 4 Assigned
Wed: HW3 Due
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Mar 24,26
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Spring Break
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Mar 31
April 2
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Week of Midterm
(Mon: Review Lecture)
(Wed: In class midterm)
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Mon: HW4 Assigned, HW 4 Due
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Midterm
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Apr 7,9
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Synchronous Circuits Advanced
6.1-6.5
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Fri: Lab 4 Due,
Lab 5 Assigned
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Apr 14,16
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Digital System Design
Instructor Notes
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Mon: HW 5 Assigned; HW 4 Due
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Apr 21,23
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Digital System Design Continued: Simple Processor
Instructor Notes
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Fri: Lab 5 Due;
Lab 6 Assigned
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Apr 28,30
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Optimized Implementations of Digital Circuits
3.4, 3.6, 8.1, 8.2
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Mon: HW 6 Assigned; HW 5 Due
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May 5
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Review and Advanced Topics
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Fri: HW 6 Due
Fri: Lab 6 Due
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May 7-
May 13
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Final Exam Based on University Schedule
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Course Policies:
● Lectures: All lectures will be in person.
● TA Help: The TAs are available to help you during their office hours, including help on both the lecture material and labs. Please make use of this resource.
● We will use NYU Brightspace for (1) to post course-related resources, examples, HWs, labs, lecture recordings; and (2) for lab/HW submissions (3) grades and (4) communicating with your classmates and with us, the teaching team.
● Labs: The Labs will be done in teams of 3. Each team will be assigned a computer that they can log in to remotely to access software tools. You can then do the labs on your own time. We will be releasing tutorial videos to help you with the labs.